Power saving data storage circuit, data writing method in the same, and data storage device

ABSTRACT

It is an object to provide, in a data storage circuit for storing data, a power saving data storage circuit and a data writing method in the data storage circuit, and, further, to provide a data storage device. Thus, in the present invention, reading out existing data stored in a storage element M is performed prior to performing writing of new data to the storage element M to compare the existing data and the new data. The data storage circuit is configured so that in a case where the existing data and the new data are identical with each other, writing to the storage element M is not performed, and, in a case where the existing data and the new data are not identical with each other, writing of the new data to the storage element M is performed. The data storage circuit is formed on a semiconductor substrate to have a data storage device.

TECHNICAL FIELD

The present invention relates to a data storage circuit for storingpredetermined data, a data writing method in the data storage circuit,and a data storage device.

BACKGROUND ART

Conventionally, in electronic computers including personal computers, adata storage circuit composed of a combination of a large number ofstorage elements is provided in a semiconductor device such as a CPU anda memory IC. Data are stored in the data storage circuit so as toexecute various types of processing.

The storage elements in such a data storage circuit are normallyconfigured so that 1-bit data is stored in each of the storage elements.More specifically, the storage element is capable of keeping twodifferent states. When one state is represented by “0” and the otherstate by “1”, data of “0” or “1” is stored by keeping any one of thestates. A large number of such storage elements are provided to enablethe storage of data in an amount corresponding to the number of providedstorage elements.

Storage elements having a wide variety of structures are known as suchstorage elements. For example, a storage element of a flash memory,which consists of a N-channel MOSFET (Metal Oxide Silicon Field EffectTransistor), is capable of storing data “0” and “1” while a state wherecharges are accumulated in a floating gate layer provided for a gateelectrode section is represented by “1” and a state where no charge isaccumulated in the floating gate layer is represented by “0” or viceversa.

A storage element of a MRAM (Magnetic Random Access Memory), whichconsists of a ferromagnetic tunnel junction element, is capable ofstoring data “0” and “1” while a state where the direction ofmagnetization of a free magnetization layer is anti-parallel to that ofa fixed magnetization layer is represented by “1” and a parallel stateby “0” or vice versa.

In a data storage circuit provided with these storage elements, in acase where data of “0” or “1” is newly stored in a certain storageelement, a state of change is induced by application of a predeterminedvoltage to the storage element or by allowing a current to passtherethrough. At this time, the storage element is forced into apredetermined state by application of a predetermined voltage to thestorage element or by allowing a current to pass therethrough,regardless of whether existing data that is previously stored in thestorage element is “0” or “1”, thereby storing new data.

In a data storage device consisting of a semiconductor device includingthe conventional data storage circuit described above, however, new datais written by application of a voltage to the storage element or byallowing a current to pass therethrough even though the previouslystored existing data and the new data to be written are identical.Therefore, there is a problem that substantially ineffective powerconsumption is generated which hinders power saving.

In particular, the storage element used for the flash memory or the MRAMdescribed above requires a considerable amount of electric power in viewof its structure to cause a change of state in order to write new data.Therefore, wasteful power consumption is increased in the data storagecircuit, such as the flash memory or the MRAM, by the correspondingamount to further hinder power saving.

DISCLOSURE OF THE INVENTION

Therefore, in order to solve the above problems, a data storage circuitof the present invention is configured to have a comparison section forreading out existing data stored in a storage element to compare theexisting data and new data with each other prior to writing of the newdata to the storage element, and so that, in the comparison section, ifthe exiting data and the new data are identical with each other, thewriting to the storage element is not performed, and if the existingdata and the new data are not identical with each other, the new data iswritten to the storage element.

The data storage circuit is also characterized by including a controlsignal generating section for generating a readout control signal forperforming readout control of the existing data and a write controlsignal for performing write control of the new data, and beingconfigured so that the existing data and the new data are compared witheach other in the comparison section in accordance with the controlsignal from the control signal generating section.

According to a data writing method in the data storage circuit of thepresent invention, it is arranged so that readout processing for readingout existing data stored in a predetermined storage element is performedprior to write processing of new data to the storage element so as tocompare the exiting data and the new data with each other, and if theexisting data and the new data are identical with each other, the writeprocessing to the storage element is not performed, and if the data notidentical, the write processing of the new data to the storage elementis performed.

Furthermore, the data writing method is also characterized by generatinga readout control signal and a write control signal in accordance with awrite signal input to the data storage circuit so as to read out theexisting data in accordance with the readout control signal and tocompare it with the new data in accordance with the write controlsignal.

In order to solve the above problems, a data storage device of thepresent invention is provided with a comparison section for reading outexisting data stored in a storage element to compare the existing dataand new data with each other prior to writing of the new data to thestorage element, and the device is configured so that, in the comparisonsection, if the exiting data and the new data are identical with eachother, the writing to the storage element is not performed, and if theexisting data and the new data are not identical with each other, thenew data is written to the storage element.

Furthermore, the data storage device is also characterized by beingprovided with a control signal generating section for generating areadout control signal for performing readout control of the existingdata and a write control signal for performing write control of the newdata, and in that the existing data and the new data are compared witheach other in the comparison section in accordance with the controlsignal from the control signal generating section.

Moreover, the data storage device is also characterized in that thecomparison section thereof is provided with: a new data retentionsection for temporarily retaining the new data; an existing dataretention section for temporarily retaining the existing data; and awrite enable signal generating section for comparing the new dataretained in the new data retention section and the exiting data retainedin the existing data retention section with each other to control anoutput of the write enable signal, and the new data is temporarilyretained in the new data retention section while the existing data istemporarily retained in the exiting data retention section in accordancewith the readout control signal output from the control signalgenerating section so as to compare the new data retained in the newdata retention section and the existing data retained in the existingdata retention section with each other in accordance with the writecontrol signal output from the control signal generating section.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a data storage circuit according tothe present invention.

FIG. 2 is a circuit diagram explaining a configuration of a controlsignal generating section.

FIG. 3 is an explanatory view of a readout control signal and a writecontrol signal generated at the control signal generation section.

FIG. 4 is a circuit diagram explaining a configuration of a comparisonsection.

FIG. 5 is a flow chart of a data writing process in the data storagecircuit.

BEST MODE FOR CARRYING OUT THE INVENTION

A data storage circuit and a data storage device formed so as to includethe data storage circuit according to the present invention respectivelyinclude a storage section consisting of a combination of a plurality ofstorage elements. If data is written to the data storage circuit and thedata storage device, existing data already stored in a predeterminedstorage element is read out in advance before new data is stored in thestorage element so as to compare the existing data and the new data witheach other. If they are identical with each other, the new data is notwritten; only if the dates are not identical with each other, the newdata is written.

More specifically, in a case where it is not necessary to induce achange of state in the storage element because the existing data and thenew data are identical with each other, a voltage is not applied to thestorage element or a current is not allowed to pass therethrough. As aresult, power consumption can be reduced by the corresponding amount toachieve a power saving.

In particular, since a probability that the existing data and the newdata will be identical with each other is about 50%, the power requiredto write the data to the storage element can be approximately halved,which greatly contributes to the power saving of the data storagecircuit and the data storage device.

The data storage device is formed by providing the data storage circuiton a semiconductor substrate. In the following description, anexplanation regarding the data storage circuit provided on thesemiconductor substrate also serves as an explanation regarding the datastorage device.

However, the data storage circuit is not limited to those provided onthe semiconductor substrate; it may be provided on an appropriatesubstrate other than the semiconductor substrate. Furthermore, thestructural form of the data storage device is not limited to that inwhich the data storage circuit is provided on a single semiconductorsubstrate; necessary circuits may be provided on a plurality ofsemiconductor substrates so as to be connected through an appropriateelectric wiring.

A comparison for determining if the exiting data and the new data areidentical with each other or not is performed in the comparison sectionprovided in the data storage circuit. After the existing data and thenew data are fetched into the comparison section, comparison processingis executed.

Furthermore, a control signal generating section for detecting a writesignal so as to generate a control signal described below is provided inthe data storage circuit. The write signal is a so-called write enablesignal. By detecting the write signal in the control signal generatingsection, the new data can be written to a predetermined storage elementin accordance with a new data signal input from a new data input lineconnected to the data storage circuit.

In particular, the control signal generating section generates a readoutcontrol signal for performing readout control of the existing data and awrite control signal for performing write control of the new data as aresult of the detection of the write signal.

Then, the control signal generating section first outputs the readoutcontrol signal so as to read out the existing data in the predeterminedstorage element and to fetch it into the comparison section.Subsequently, the control signal generating section outputs the writecontrol signal to compare the existing data and the new data fetchedinto the comparison section with each other. If the existing data andthe new data are not identical with each other, the comparison sectionoutputs the write enable signal so as to execute writing of the new datato the storage element.

On the other hand, if the existing data and the new data are identicalwith each other, the comparison section does not output the write enablesignal. Accordingly, the writing of new data to the storage element isnot executed, so that wasteful power consumption is suppressed.

An embodiment of the present invention will be described in detail belowwith reference to the drawings.

FIG. 1 is a block diagram showing a data storage circuit 1 according tothis embodiment. The data storage circuit 1 includes: a storage section3 having a storage element area 2 in which a plurality of storageelements M are appropriately arranged; a control signal generatingsection 4 for detecting a write signal 7 s that brings the storagesection 3 into an input receiving state of new data; and a comparisonsection 5 for performing write control of the new data, which is storedin a predetermined one of the storage elements M of the storage section3, to the storage element M in accordance with the detection of thewrite signal 7 s.

Furthermore, to the data storage circuit 1, a new data input line 6 forinputting the new data to the storage section 3 is connected while awrite signal line 7 for inputting a write signal 7 s to the controlsignal generating section 4 is also connected.

In this embodiment, a ferromagnetic tunnel junction element is used aseach of the storage elements M. The ferromagnetic tunnel junctionelements are provided at the crossing points between a plurality of wordlines 8 and bit lines 9 provided in a grid pattern in the storageelement area 2. Although not shown, sense lines for reading-out areprovided in parallel to the word lines 8 so as to read out data storedin the ferromagnetic tunnel junction elements.

Although the following description is given for a case where the storageelement M is a ferromagnetic tunnel junction element, the storageelement M is not limited to the ferromagnetic tunnel junction element. Aknown storage element, such as a N-channel MOSFET constituting a flashmemory may also be used. In this case, the word lines 8 and the bitlines 9 may be appropriately provided in accordance with a writing modeand a reading-out mode of the data to/from the storage elements M.

Column drive control sections 10 are connected to an end of each of theword lines 8 and an end of each of the sense lines. Each of the columndrive control sections 10 is connected to a column decoder 11 so as tooperate in accordance with a control signal from the column decoder 11.Moreover, a row drive control section 12 is connected to an end of eachof the bit lines 9. Each of the row drive control sections 12 isconnected to a row decoder 13 so as to operate in accordance with acontrol signal from the row decoder 13.

A column address data output section 14 is connected to the columndecoder 11, whereas a row address data output section 15 is connected tothe row decoder 13. An external input signal for specifying apredetermined one of the storage elements M is configured to be inputfrom the column address data output section 14 to the column decoder 11as a column address data signal 14 s and to be input from the rowaddress data output section 15 to the row address decoder 13 as a rowaddress data signal 15 s.

Although it is depicted in FIG. 1 that the column address data outputsection 14 and the row address data output section 15 are providedoutside of the data storage circuit 1, the data storage circuit 1 may beconfigured to include the column address data output section 14 and therow address data output section 15.

The column decoder 11 performs decoding in accordance with the inputcolumn address data signal 14 s so as to operate any one of the columndrive control sections 10 connected to the column decoder 11. The rowdecoder 13 performs decoding in accordance with the input row addressdata signal 15 s so as to operate any one of the row drive controlsections 12 connected to the row decoder 13. The storage element M,which is positioned at a crossing point between the word line 8 or thesense line connected to the column drive control section 10 currentlybeing operated and the bit line 9 connected to the row drive controlsection 12 similarly currently being operated, is brought into anoperating state so as to enable the write/readout of data to/from thestorage element M.

In particular, in a case of writing new data to the storage element M orin a case of reading out existing data from the storage element M, thecolumn address data signal 14 s output from the column address dataoutput section 14 and the row address data signal 15 s output from therow address data output section 15 bring the storage element M, to/fromwhich writing or reading-out is performed, into an operating state inadvance.

Furthermore, since the ferromagnetic tunnel junction element is used asthe storage element M in this embodiment, the new data input lines 6 areconnected to the row drive control sections 12, respectively. Then, thepredetermined storage element M is brought into an operating state asdescribed above and a new data signal 6 s is input to the row drivecontrol section 12 through the new data input line 6, so that the rowdrive control section 12 allows a current to pass through the bit line 9in a predetermined direction, thereby writing the new data to thestorage element M.

On the other hand, for reading out the existing data stored in thestorage element M, the storage element M, from which reading-out isperformed, is brought into an operating state as described above. Aresistance value of the storage element M is detected by using the senseline so as to generate an existing data signal in accordance with theresistance value detected in the column drive control section 10 and tooutput it to the column decoder 11.

The data storage circuit 1 is normally in a protected state where astorage state in the storage element M is prevented from beingautomatically varied by an erroneous input of a noise and the like. Byinputting the write signal 7 s to the data storage circuit 1 as 20,described above, the storage section 3 of the data storage circuit 1allows the input of the new data only when the write signal 7 s is inputto enable the writing of the new data.

In particular, with the detection of the write signal 7 s, a readoutcontrol signal 16 s and a write control signal 17 s are generated in thecontrol signal generating section 4 for detecting the write signal 7 sin the data storage circuit 1. The readout control signal 16 s is acontrol signal for performing reading-out of the existing data from thestorage element M to which the new data is to be stored. The writecontrol signal 17 s is a control signal for performing writing of thenew data to the storage element M.

As shown in FIG. 2, a readout control signal generating section 18 and awrite control signal generating section 19 are provided in parallel inthe control signal generating section 4 so as to generate the readoutcontrol signal 16 s and the write control signal 17 s from the writesignal 7 s.

More specifically, in the control signal generating section 4, the writesignal line 7 is branched into a readout control signal generating line20 and a write control signal generating line 21 so as to input thewrite signal 7 s to the readout control signal generating section 18 andthe write control signal generating line 19, respectively. In thismanner, the readout control signal 16 s is generated in the readoutcontrol signal generating section 18, whereas the write control signal17 s is generated in the write control signal generating section 19.

In the readout control signal generating section 18, the readout-controlsignal generating line 20 is further branched into a first readoutcontrol signal generating line 20 a and a second readout control signalgenerating line 20 b. The first readout control signal generating line20 a and the second readout control signal generating line 20 b areconnected to an AND gate 22 which generates the readout control signal16 s.

At this time, a NOT gate 23 is provided in the middle of the secondreadout control signal generating line 20 b. Furthermore, a resistor 24is provided on the output side of the NOT gate 23 to which an end of acapacitor 25 is connected. As a result, as shown in FIG. 3, the readoutcontrol signal generating section 18 detects a rise of the write signal7 s to generate the readout control signal 16 s so as to output it fromthe readout control signal line 16 connected to the AND gate 22.

Moreover, in the write control signal generating section 19, the writecontrol signal generating line 21 is also further branched into a firstwrite control signal generating line 21 a and a second write controlsignal generating line 21 b. The first write control signal generatingline 21 a and the second write control signal generating line 21 b areconnected to a NOR gate 26 which generates the write control signal 17s.

At this time, a NOT gate 27 is provided in the middle of the secondwrite control signal generating line 21 b. Furthermore, a resistor 28 isprovided on the output side of the NOT gate 27, to which an end of acapacitor 29 is connected. As a result, as shown in FIG. 3, the writecontrol signal generating section 19 detects a fall of the write signal17 s to generate the write control signal 17 s so as to output it fromthe write control signal line 17 connected to the NOR gate 26.

More specifically, since the readout control signal 16 s and the writecontrol signal 17 s can be generated from the same write signal 7 s, thereadout control signal 16 s and the write control signal 17 s, whichhave a predetermined difference in time therebetween, can be generatedwith good accuracy with an extremely simple structure. Therefore, thecontrol of the comparison section 5 described below by the readoutcontrol signal 16 s and the write control signal 17 s can be ensured.

As shown in FIG. 1, the readout control signal line 16 and the writecontrol signal line 17 are connected to the column decoder 11 and therow decoder 13 so as to control the column decoder 11 and the rowdecoder 13 in accordance with the readout control signal 16 s and thewrite control signal 17 s in a manner described below. Furthermore, thereadout control signal line 16 and the write control signal line 17 arerespectively connected to each of the column drive control sections 10and each of the row drive control sections 12 so as to control thecolumn drive control sections 10 and the row drive control sections 12in accordance with the readout control signal 16 s and the write controlsignal 17 s in a manner described below.

The readout control signal line 16 and the write control signal line 17are also connected to the comparison section 5 so that the readoutcontrol signal 16 s and the write control signal 17 s are input to thecomparison section 5 to control the comparison section 5.

Furthermore, the new data input line 6 and an existing data input line30 that is connected to the row decoder 11 are connected to thecomparison section 5 so as to input thereto the new data signal 6 s andan existing data signal 30 s to be compared with each other.

As shown in FIG. 4, the comparison section 5 is configured with a newdata signal retention section 31 for temporarily retaining the new datasignal 6 s input through the new data input line 6; an existing datasignal retention section 32 for temporarily retaining the existing datasignal 30 s input through the existing data input line 30; and a writeenable signal generating section 33 for comparing the new data signal 6s retained in the new data signal retention section 31 and the existingdata signal 30 s retained in the existing data signal retention section32 with each other.

The new data signal retention section 31 is configured with an inputcontrol transistor 34 for controlling an input of the new data signal 6s to the new data signal retention section 31; and a retention section35 for retaining the new data signal 6 s input to the new data signalretention section 31.

The readout control signal line 16 is connected to a gate electrode ofthe input control transistor 34. The readout control signal 16 s isinput to the gate electrode so that the new data signal 6 s is inputfrom the new data input line 6 connected to the input control transistor34 to the retention section 35 connected to the input control transistor34.

The retention section 35 is a simple storage circuit consisting of alatch composed of the combination of two inverters 36, which is capableof retaining the new data signal 6 s for a certain period of time.

Similarly to the new data signal retention section 31, the existing datasignal retention section 32 is also configured with an input controltransistor 37 for controlling an input of the existing data signal 30 sto the existing data signal retention section 32; and a retentionsection 38 for retaining the existing data signal 30 s input to theexisting data signal retention section 32.

The readout control signal line 16 is connected to a gate electrode ofthe input control transistor 37. The readout control signal 16 s isinput to the gate electrode so that the existing data signal 30 s isinput from the existing data input line 30 connected to the inputcontrol transistor 37 to the retention section 38 connected to the inputcontrol transistor 37.

The retention section 38 is a simple storage circuit consisting of alatch composed of a combination of two inverters 40, 40, which iscapable of retaining the existing data signal 30 s for a certain periodof time.

The write enable signal generating section 33 is configured with anoutput control transistor 41 for controlling an output of the new datasignal 6 s from the new data signal retention section 31; an outputcontrol transistor 42 for controlling an output of the existing datasignal 30 s from the existing data signal retention section 32; and anXOR gate 43 for inputting the new data signal 6 s and the existing datasignal 30 s output respectively from the retention sections 35 and 38 bythe output control transistors 41 and 42 thereto.

In particular, the write control signal line 17 is connected to gateelectrodes of the output control transistors 41 and 42, respectively.The write control signal 17 s is input to the output control transistors41 and 42 through the write control signal line 17 so as to output thenew data signal 6 s and the existing data signal 30 s from the retentionsections 35 and 38 to the XOR gate 43.

In a case where the input new data signal 6 s and the existing datasignal 30 s are not identical with each other, the XOR gate 43 outputsthe write enable signal 44 s from the write enable signal line 44connected to the XOR gate 43. In a case where the new data signal 6 sand the existing data signal 30 s are identical with each other, it doesnot output the write enable signal 44 s.

It is possible to extremely easily compare the new data signal 6 s andthe existing data signal 30 s by inputting the write control signal 17 sto the gate signals of the output control transistors 41 and 42 and tosimultaneously output the new data signal 6 s and the existing datasignal 30 s from the new data signal retention section 31 and theexisting data signal retention section 32. As a result, it is possibleto simplify the structure of the write enable signal generating section33.

Furthermore, since determination processing in the write enables signalgenerating section 33 can be performed within a short period of time, aprocessing speed can be improved.

Except for the time of inputting the write control signal 17 s, anerroneous operation protect signal is input to the XOR gate 43 so as toprevent the XOR gate 43 from erroneously outputting the write enablesignal 44 s. In this embodiment, the control transistors 41, 42 and 45,each having the gate electrode to which the write control signal line 17is connected, are used to control the erroneous operation protectsignal.

As shown in FIG. 1, the write enable signal line 44 is configured sothat it is connected to each of the column drive control sections 10 andeach of the row drive control sections 12 so as to input the writeenable signal 44 s to each of the column drive control sections 10 andeach of the row drive control sections 12.

Finally, in accordance with a flowchart of FIG. 5, an operation forstoring the new data in the data storage circuit 1 configured asdescribed above will be described. When the new data is to be stored inthe predetermined storage element M, the storage element M is broughtinto an operation state in advance as described above (step S1).

Then, to the data storage circuit 1, the new data signal 6 s is inputfrom the new data input line 6 (step S2) while the write signal 7 s isinput from the write signal line 7 (step S3).

In accordance with the input of the write signal 7 s, the control signalgenerating section 4 first outputs the readout control signal 16 sthrough the readout control signal line 16 (step S4) so as to input itto the column decoder 11, the row decoder 13, each of the column drivecontrol sections 10, and each of the row drive control sections 12,thereby reading out the existing data stored in the predeterminedstorage element M to the column decoder 11. The column decoder 11outputs the readout existing data as the existing data signal 30 s tothe existing data input line 30 connected to the column decoder 11 (stepS5). This corresponds to readout processing.

The control signal generating section 4 also inputs the readout controlsignal 16 s to the comparison section 5. In the comparison section 5, inresponse to the input of the readout control signal 16 s, the new datasignal 6 s is input to the new data signal retention section 31 of thecomparison section 5 so as to be temporarily retained therein, whereasthe existing data signal 30 s is input to the existing data signalretention section 32 so as to be temporarily retained therein (step S6).

After a predetermined period of time, the control signal generatingsection 4 generates the write control signal 17 s in accordance with thewrite signal 7 s so as to input the write control signal 17 s to thecomparison section 5 (step S7). The write control signal 17 s regulatesthe write signal 7 s so that it is output from the control signalgenerating section 4 after an elapse of a sufficient period of time toinput the new data signal 6 s and the existing data signal 30 s to thecomparison section 5 by the readout control signal 16 s.

The comparison section 5 outputs and compares the new data signal 6 sretained in the new data signal retention section 31 and the exitingdata signal 30 s retained in the existing data signal retention section32 in accordance with the input write control signal 17 s (step S8).

In a case where the new data signal 6 s and the existing data signal 30s are not identical with each other, it means the new data and theexisting data are different from each other. Therefore, the comparisonsection 5 outputs the write enable signal 44 s (step S9).

At this time, the write control signal 17 s output from the controlsignal generating section 4 is also input to the column decoder 11, therow decoder 13, each of the column drive control sections 10 and each ofthe row drive control sections 12 through the write control signal line17. Furthermore, the write enable signal 44 s output from the comparisonsection 5 is input to each of the column drive control sections 10 andeach of the row drive control sections 12 through the write enablessignal line 44, so that the storage section 3 writes the new data to thepredetermined storage element M (step S10). This corresponds to writeprocessing.

On the other hand, in the comparison between the new data signal 6 s andthe existing data signal 30 s in the comparison section 5 (step S8), ina case where the new data signal 6 s and the existing data signal 30 sare identical with each other, that is, in a case where the new data andthe existing data are identical with each other, the comparison section5 does not output the write enable signal 44 s. The write processing isterminated while the storage section 3 does not write the new data tothe predetermined storage element M.

Since the existing data already stored in the storage element M is thesame as the new data even if the new data is not written to the storageelement M, no problem arises.

As described above, in a case where the new data to be stored in thestorage element M is identical with the existing data already stored inthe storage element M to which the new data is to be written, the newdata is not written. As a result, the power consumption, which wouldotherwise be generated by writing the new data, can be reduced, therebyachieving a power saving.

By providing the above-described data storage circuit 1 on asemiconductor substrate, a data storage device achieving a powerreduction can be formed. By using the data storage device, a CPUincluding an IC memory or a storage area with a power reduction can beformed.

INDUSTRIAL APPLICABILITY

(1) In an embodiment of the present invention, by providing a comparisonsection for reading out existing data stored in a storage element tocompare the existing data and new data with each other prior to writingof the new data to the storage element, and configuring so that, in thecomparison section, in a case where the exiting data and the new dataare identical with each other, the writing to the storage element is notperformed, and in a case where the existing data and the new data arenot identical with each other, the new data is written to the storageelement, it is possible to substantially reduce the number of times ofexecution of writing to the storage element so that power consumptionbrought by the writing of the new data can be suppressed to accomplishpower saving.

In particular, since a probability that the existing data and the newdata will be identical with each other is about 50%, the power requiredto write the data to the storage element can be approximately halved.

(2) According to an embodiment of the invention, by providing the datastorage circuit with a control signal generating section for generatinga readout control signal for performing readout control of the existingdata and a write control signal for performing write control of the newdata, and by configuring the data storage circuit so that the existingdata and the new data are compared with each other in the comparisonsection in accordance with the control signal from the control signalgenerating section, the readout control signal and the write controlsignal generated with good accuracy can surely perform control of thedata storage circuit and avoid erroneous operation to prevent excesspower consumption. In particular, it is possible to adjust a timedifference between the readout control signal and the write controlsignal generated with a predetermined time difference therebetween to beminimal so that the processing at the comparison section can beperformed at high speed.

(3) According to an embodiment of the invention as described in claim 3,by performing a readout process of existing data stored in a storageelement prior to performing a write process of the new data to thestorage element to compare the existing data and the new data with eachother so as not to perform the writing to the storage element in a casewhere the exiting data and the new data are identical with each otherand so as to perform writing of the new data to the storage element in acase where the existing data and the new data are not identical witheach other, similarly to the invention as described in claim 1, it ispossible to substantially reduce the number of times of execution ofwriting to the storage element so that power consumption brought by thewriting of the new data can be suppressed to accomplish a power savingbecause the writing is not performed in a case of the existing data andthe new data being identical to each other.

(4) According to an embodiment of the invention, by generating a readoutcontrol signal and a write control signal in accordance with a writesignal input to the data storage circuit and by reading out the existingdata in accordance with the readout control signal to compare theexisting data with the new data in accordance with the write controlsignal, it is possible to perform the write processing of the new dataimmediately subsequent to the readout processing of the existing data sothat processing speed can be improved and erroneous operation is avoidedto prevent excess power consumption.

(5) According to an embodiment of the invention, by providing acomparison section for reading out existing data stored in a storageelement to compare the existing data and new data with each other priorto writing of the new data to the storage element, and configuring sothat, in the comparison section, in a case where the existing data andthe new data are identical with each other, the writing to the storageelement is not performed, and in a case where the existing data and thenew data are not identical with each other, the new data is written tothe storage element, similarly to the invention as described in claim 1,it is possible to substantially reduce the number of times of executionof writing to the storage element so that power consumption brought bythe writing of the new data can be suppressed to accomplish a powersaving.

(6) According to an embodiment of the invention, by providing the datastorage device with a control signal generating section for generating areadout control signal for performing readout control of the existingdata and a write control signal for performing write control of the newdata, and by configuring the data storage circuit so that the existingdata and the new data are compared with each other in the comparisonsection in accordance with the control signal from the control signalgenerating section, similarly to the invention as described in claim 2,the readout control signal and the write control signal generated withgood accuracy can surely perform control of the data storage circuit andavoid erroneous operation to prevent excess power consumption. Inparticular, it is possible to adjust a time difference between thereadout control signal and the write control signal generated with apredetermined time difference therebetween to be minimal so that theprocessing at the comparison section can be performed at a high speed.

(7) According to an embodiment of the invention, by providing thecomparison section with a new data retention section for temporarilyretaining the new data; an existing data retention section fortemporarily retaining the existing data; and a write enable signalgenerating section for comparing the new data retained in the new dataretention section and the exiting data retained in the existing dataretention section with each other to control an output of the writeenable signal, and configuring so that the new data is temporarilyretained in the new data retention section while the existing data istemporarily retained in the exiting data retention section in accordancewith the readout control signal output from the control signalgenerating section so as to compare the new data retained in the newdata retention section and the existing data retained in the existingdata retention section with each other in accordance with the writecontrol signal output from the control signal generating section, it ispossible to compare the new data and the existing data after correctlyobtaining them, respectively, so as to avoid an erroneous operation sothat excessive power consumption can be prevented.

1. A data storage circuit comprising: a comparison section for readingout existing data stored in a storage element to compare said existingdata and new data with each other prior to writing of said new data tosaid storage element, wherein: when the comparison section determinesthat the existing data and the new data are identical, the new data isnot written to the storage element, and when the comparison sectiondetermines that the existing data and the new data are not identical,the new data is written to the storage element; and a control signalgenerating section for generating a readout control signal and a writecontrol signal from a write signal input to said control signalgenerating section, said readout control signal for performing readoutcontrol of the existing data and said write control signal forperforming write control of the new data, wherein the existing data andthe new data are compared with each other in the comparison section inaccordance with the write control signal from the control signalgenerating section; wherein said control signal generating sectionincludes an AND logic gate for generating said readout control signal,and a NOR logic gate for generating said write control signal; andwherein the pulse of the readout control signal and write control signalare shorter than the pulse of the write signal input to said controlsignal generating section.
 2. A method for writing data in a datastorage circuit, comprising: reading out existing data stored in astorage element prior to writing new data to the storage element tocompare the existing data and the new data to each other; writing thenew data to the storage element when the existing data and said new dataare identical with each other, and so as to perform the write process ofsaid new data to said storage element in a case where said existing dataand said new data are not identical with each other; and generating areadout control signal and a write control signal in accordance with awrite signal input to the data storage circuit; reading out the existingdata in accordance with the readout control signal; and comparing theexisting data with the new data in accordance with the write controlsignal; wherein said generating step includes using an AND logic gate togenerate said readout control signal, and a NOR logic gate to generatesaid write control signal; and wherein the pulse of the generatedreadout control signal and write control signal are shorter than thepulse of the write signal input to the data storage circuit.
 3. A datastorage device comprising: a comparison section for reading out existingdata stored in a storage element and compare the existing data and newdata to each other prior to writing the new data to the storage element,wherein when the comparison section determines that the existing dataand new data are identical, the new data is not written to the storageelement, and when the comparison section determines that the existingdata and new data are not identical, the new data is written to thestorage element; a control signal generating section for generating areadout control signal and a write control signal from a write signalinput to said control signal generating section, said readout controlsignal for performing readout control of the existing data and a writecontrol signal for performing write control of the new data, wherein theexisting data and the new data are compared to each other in thecomparison section, in accordance with a control signal from saidcontrol signal generating section; wherein said control signalgenerating section includes an AND logic gate for generating saidreadout control signal, and a NOR logic gate for generating said writecontrol signal; and wherein the pulse of the readout control signal andwrite control signal are shorter than the pulse of the write signalinput to said control signal generating section.
 4. The data storagedevice as described in claim 3, wherein the comparison sectioncomprises: a new data retention section for temporarily retaining thenew data; an existing data retention section for temporarily retainingthe existing data; and a write enable signal generating section forcomparing the new data retained in the new data retention section andthe existing data retained in the existing data retention section witheach other to control an output of the write enable signal, wherein, thenew data is temporarily retained in the new data retention section whilethe existing data is temporarily retained in the existing data retentionsection in response to the readout control signal output from thecontrol signal generating section, and the new data retained in the newdata retention section and the existing data retained in the existingdata retention section are compared to each other in response to thewrite control signal output from the control signal generating section.5. The data storage device according to claim 4, wherein said new dataretention section and existing data retention section include inputcontrol transistors for controlling the retaining of the new data andthe existing data in accordance with readout control signal.
 6. The datastorage device according to claim 4, wherein the write enable signalgeneration section includes output control transistors for controllingcomparison of the new data and the existing data in accordance with thewrite control signal.
 7. The data storage device according to claim 4,wherein the write enable signal generation section includes an XOR logicgate for generating a write enable signal in accordance with the newdata and the existing data.